document no. 70-0266-03 www.psemi.com page 1 of 7 ?2008-2012 peregrine semiconductor corp. all rights reserved. 32-lead 5x5x0.85 mm figure 2. package type the following specification defines an spdt (single pole double throw) switch for use in cellular and other wireless applications. the pe42510a uses peregrine?s ultracmos ? process and it also features harp? technology enhancements to deliver high linearity and exceptional harmonics performance. harp? technology is an innovative feature of the ultracmos ? process providing upgraded linearity performance. the pe42510a is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt high power ultracmos ? reflective rf switch 30 - 2000 mhz product description figure 1. functional diagram pe42510a features ?? no blocking capacitors required ?? 50 watt p1db compression point ?? 10 watts <8:1 vswr ( normal operation ) ?? 29 db isolation @ 800 mhz ?? <0.3 db insertion loss at 800 mhz ?? 2f o and 3f o < -84 dbc @ 42.5 dbm ?? esd rugged to 2.0 kv hbm ?? 32-lead 5x5x0.85 mm qfn package table 1. electrical specifications @ 25c, v dd = 3.3v (z s = z l = 50 ? ) unless otherwise noted parameter conditions min typ max units rf insertion loss 30 mhz 1 ghz 1 ghz < 2 ghz 0.4 0.5 0.6 0.7 db db 0.1 db input compression point 800 mhz, 50% duty cycle 45.4 dbm isolation (supply biased): rf to rfc 800 mhz 25 29 db unbiased isolation: rf - rfc, v dd , v1=0v 27 dbm, 800 mhz 5 db rf (active port) return loss 15 22 db 2nd harmonic 3rd harmonic 800 mhz @ +42.5 dbm -84 -81 dbc switching time 2,3 50% of ctrl to 10/90% of rf 25 31 s notes: 1. the device was matched with 1.6 nh inductance per rf port 2. for high power applications, harmonics settling needs to be accounted for. harmonics settling time is defined to be 50% of ctrl to 2fo/3fo within 3 db of final value 3. for rf input power (50 ? ) > 31 dbm, and operation above 30 mhz, the switching time and harmonics settling time is 100 s max 71-0014 obsolete
product specification pe42510a page 2 of 7 ?2008-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0266-03 ultracmos ? rfic solutions 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 gnd rf1 gnd gnd gnd gnd gnd gnd gnd rf2 gnd gnd gnd gnd gnd gnd gnd gnd n/c v dd ctrl gnd gnd n/c gnd gnd gnd gnd rfc gnd gnd gnd exposed ground paddle table 2. pin descriptions table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 3. operating ranges figure 3. pin configuration (top view) pin no. pin name description 1 gnd ground 2 rf1 rf1 port 3 gnd ground 4 gnd ground 5 gnd ground 6 gnd ground 7 gnd ground 8 gnd ground 9 gnd ground 10 gnd ground 11 n/c no connect 12 v dd nominal 3.3 v supply connection 13 ctrl control 14 gnd ground 15 gnd ground 16 n/c do not connect 17 gnd ground 18 gnd ground 19 gnd ground 20 gnd ground 21 gnd ground 22 gnd ground 23 rf2 rf2 port. 24 gnd ground 25 gnd ground 26 gnd ground 27 gnd ground 28 rfc common rf port for switch 29 gnd ground 30 gnd ground 31 gnd ground 32 gnd ground paddle gnd exposed ground paddle absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. table 5. control logic truth table symbol parameter/conditions min max units v dd power supply voltage -0.3 4 v v i voltage on any dc input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t case maximum case temperature 85 c t j peak maximum junction temperature (10 seconds max) 200 c p in rf input power (vswr 20:1, 10 seconds) 40 dbm rf input power (50 ? ) 45 dbm rf input power, unbiased (vswr 20:1) 27 dbm p d maximum power dissipation due to rf insertion loss 2.2 w v esd esd voltage (hbm, mil_std 883 method 3015.7) 2000 v parameter min typ max units v dd power supply voltage 3.2 3.3 3.4 v i dd power supply current 90 170 a control voltage high 1.4 v control voltage low 0.4 v operating temperature range (case) -40 85 c t j operating junction temperature 140 c frequency range 30 2000 mhz rf input power 1 (vswr 8:1) 40 dbm rf input power 2 (vswr 8:1) 27 dbm path ctrl rfc ? rf1 h rfc ? rf2 l moisture sensitivity level the moisture sensitivity level rating for the 5x5x0.85 mm qfn package is msl3. notes: 1. supply biased 2. supply unbiased obsolete
product specification pe42510a page 3 of 7 document no. 70-0266-03 www.psemi.com ?2008-2012 peregrine semiconductor corp. all rights reserved. evaluation kit the pe42510a evaluation kit board was designed to ease customer evaluation of the pe42510a rf switch. dc power is supplied through j10, with v dd on pin 9, and gnd on the entire lower row of even numbered pins. to evaluate a switch path, add or remove jumpers on ctrl/v1 (pin 3) using table 5 (adding a jumper pulls the cmos control pin low and removing it allows the on-board pull-up resistor to set the cmos control pin high). j10 pins 1, 11, and 13 are n/c. the rf common port (rfc) is connected through a 50? transmission line via t he top sma connector, j1. rf1 and rf2 paths ar e also connected through 50 ? transmission lines via sma connectors. a 50 ? through transmission line is available via sma connectors j8 and j9. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. an open- ended 50 ? transmission line is also provided at j7 for calibration if needed. figure 4. evaluation board layouts figure 5. evaluation board schematic 102-0383-02 101-0314-02 obsolete
product specification pe42510a page 4 of 7 ?2008-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0266-03 ultracmos ? rfic solutions figure 7. rf-rfc insertion loss, +25c figure 6. rf-rfc insertion loss, v dd = 3.3v figure 8. rfc-rf isolation, v dd = 3.3v figure 9. rfc-rf isolation, +25c figure 11. rf return loss, +25c figure 10. rf return loss, v dd = 3.3v obsolete
product specification pe42510a page 5 of 7 document no. 70-0266-03 www.psemi.com ?2008-2012 peregrine semiconductor corp. all rights reserved. figure 12. power dissipation figure 13. maximum junction temperature thermal data though the insertion loss for this part is very low, when handling high power rf signals, the part can get quite hot. figure 12 shows the estimated power dissipation for a given incident rf power level. multiple curves are presented to show the effect of poor vswr conditions. vswr conditions that present short circuit loads to the part can cause significantly more power dissipation than with proper matching. figure 13 shows the estimated maximum junction temperature of the part for similar conditions. note that both of these char ts assume that the case (gnd slug) temperature is held at 85c. special consideration needs to be m ade in the design of the pcb to properly dissipate the heat away from the part and maintain the 85c maximum case temperature. it is recommended to use best design practices for high power qfn packages: multi-layer pcbs with thermal vias in a thermal pad soldered to the slug of the package. special care also needs to be made to alleviate solder voiding under the part. table 6. theta jc parameter min typ max units theta jc (+85c) 24.0 c/w 85 90 95 100 105 110 115 120 125 130 135 140 145 30 31 3 2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 rf power (dbm) 1:1 vswr (50 ohm load) 2:1 vswr (25 ohm load) 8:1 vswr (6.25 ohm load) 20:1 vswr (2.5 ohm load) inf:1 vswr (0 ohm load) reliability limit 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 gnd rf1 gnd gnd gnd gnd gnd gnd gnd rf2 gnd gnd gnd gnd gnd gnd gnd gnd n/c v dd ctrl gnd gnd n/c gnd gnd gnd gnd rfc gnd gnd gnd exposed ground paddle note: case temperature = 85c max junction temperature (c) obsolete
product specification pe42510a page 6 of 7 ?2008-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0266-03 ultracmos ? rfic solutions figure 14. package drawing see note below note: not for electrical connection. corner detail is tied to paddle and should not be isolated on pcb board figure 14. top marking specification = pin 1 designator 42510a = six digit part number yyww = date code, last two digits of the year and work week zzzzzz = six digits of the lot number 42510a yyww zzzzzz 17-0091-01 19-0146 obsolete
product specification pe42510a page 7 of 7 document no. 70-0266-03 www.psemi.com ?2008-2012 peregrine semiconductor corp. all rights reserved. advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com . table 7. ordering information order code description package shipping method pe42510amli parts in tubes or cut tape green 32-lead 5x5mm qfn 73 units/tube pe42510amli-x parts on tape and reel green 32-lead 5x5mm qfn 500 units/t&r ek42510-01 evaluation ki t evaluation kit 1/box figure 15. tape and reel specs ao = 5.25 0.1 mm bo = 5.25 0.1 mm ko = 1.10 0.1 mm notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole device orientation in tape top of device pin 1 tape feed direction obsolete
|
